سوال ۷۷ کنکور ارشد مهندسی کامپیوتر ۱۴۰۴

We track each signal after $A$ switches $1\to 0$ at $t=0$, accounting for the delay written inside every gate.

Branch X (lower AND, delay $5$). $X = A \land B = A \land 1 = A.$ When $A$ falls at $t=0$, the AND delay pushes the change by $5$, so $X:\ 1 \to 0 \text{ at } t = 5.$

Branch Y (upper AND, delay $5$, fed by the inverter of delay $20$). The inverter computes $\overline{A}$ with delay $20$: when $A$ falls at $t=0$, $\overline{A}$ rises $0\to 1$ at $t=20$. Then $Y = C \land \overline{A} = 1 \land \overline{A},$ so the AND ($+5$) gives $Y:\ 0 \to 1 \text{ at } t = 20 + 5 = 25.$

Node W (OR, delay $5$), which is the $D$ input. $W = Y \lor X.$

• For $t<0$: $Y=0,\ X=1 \Rightarrow W=1$.
• $X$ drops at $t=5$; with $Y$ still $0$ the OR output falls $1\to 0$ at $t = 5+5 = 10$.
• $Y$ rises at $t=25$; the OR output rises $0\to 1$ at $t = 25+5 = 30$.

So $W$ ($=D$) glitches: it is $1$ until $t=10$, sits at $0$ during $10 \le t < 30$, and is stably $1$ only from $t=30$ onward.

Sampling at the flip-flop. The DFF captures $D$ on a rising clock edge with no delay. The output $Z$ can latch to $1$ only when the clock edge samples a settled $D=1$, i.e. at $t = 30.$

Hence $Z$ becomes $1$ at $t=30$ — option (3).

Pitfall: Do not stop at the first time $D$ is $1$. Because $X$ falls before $\overline{A}$ rises ($5$ vs $20$ delay), $W$ collapses to $0$ for a window and only the slow $Y$ path ($20+5+5=30$) drives $D$ permanently high — that later time is what the clock must sample.