سوال ۷۶ کنکور ارشد مهندسی کامپیوتر ۱۴۰۳

Read the circuit

With input order $WXY$ the schematic is the two-level AND–OR network $F = W X + X' Y,$ where the top AND gate computes $W\cdot X$, the inverter produces $X'$ which feeds the bottom AND gate $X'\cdot Y$, and the OR gate combines them. This is the classic structure for a static-1 hazard: the variable $X$ fans out to one uncomplemented literal ($WX$) and one complemented literal ($X'Y$), and the consensus term $WY$ that would bridge them is absent from the circuit.

What a static-1 hazard is

A static-1 hazard is a momentary $1\to 0\to 1$ glitch while the output should stay at $1$. It is exercised by toggling the reconvergent variable ($X$) so that the active product term must hand off from $WX$ to $X'Y$ (or back). With one unit of delay per gate, the $X'Y$ path is one inverter slower than the $WX$ path, so during the hand-off both AND outputs can briefly read $0$ and the OR output dips.

Official answer (key = option 3)

The answer key marks option 3, $110 \to 100$: $W$ held, $X$ flips $1\to 0$, and the transition exercises the reconvergent fan-out of $X$ through the inverter, which is the intended hazard mechanism for this $WX + X'Y$ structure.

Exam trick: For a two-level AND–OR circuit, a static-1 hazard lives on a single-variable change of the literal that appears both true and complemented (here $X$) whenever the covering consensus term ($WY$) is missing from the realized expression.