سوال ۷۷ کنکور ارشد مهندسی کامپیوتر ۱۴۰۲

The block is a 4-bit synchronous UP counter with a synchronous parallel-load input. We must read the surrounding control logic.

Fixed inputs.

• The active-low clear pin is tied to 1, so the counter is never cleared.
• The parallel-load data bus is wired to $I_3I_2I_1I_0 = 0\,1\,0\,0$, i.e. the value that gets loaded is

$I = (0100)_2 = 4.$

Load-control logic. The bottom gate is a 2-input NAND fed by $Q_3$ and $Q_2$:

$g = \overline{Q_3\,Q_2}.$

Its output goes to the upper NAND, whose other input is Reset passed through an inverter, i.e. $\overline{Reset}$. So

$\text{Load} = \overline{\;\overline{Reset}\cdot \overline{Q_3 Q_2}\;}.$

During normal counting $Reset = 0 \Rightarrow \overline{Reset} = 1$, hence

$\text{Load} = \overline{\,1\cdot \overline{Q_3 Q_2}\,} = Q_3\,Q_2.$

So Load is asserted exactly when $Q_3 = Q_2 = 1$.

Trace the sequence. Once loaded with $4 = (0100)_2$, the counter increments each clock. The product $Q_3 Q_2$ first becomes $1$ at

$(1100)_2 = 12,$

because $12$ is the smallest value with both bit-3 and bit-2 high. The visited counts are therefore

$4,5,6,7,8,9,10,11,12.$

At $12$ the asserted Load forces the next clock edge to reload $4$, so the cycle repeats. The counter counts from 4 to 12, which is option 2.

Pitfall: The reload happens after the count that triggers Load (synchronous load), so $12$ itself is reached and displayed before the jump back to $4$ — the top of the range is $12$, not $11$. Also note that $15$ is never reached because the decode fires at the first value with $Q_3 Q_2 = 1$, which is $12$.