معماری کامپیوترComputer Architecture
معماری مجموعه دستورالعمل (ISA)، مسیر داده و واحد کنترل، خط لوله (Pipeline)، سلسلهمراتب حافظه و حافظهٔ نهان (Cache).
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Overall speedup is limited by the un-accelerated fraction: improve a part by dividing only its time-fraction by its local speedup, while CPU time itself is set by instruction count, average CPI, and clock period.
Split every address into tag/index/offset (offset = log2 block, index = log2 of the number of SETS), place blocks by the mapping (direct / set-associative / fully associative), evict by the replacement policy (e.g. LRU), and rate the design with the hit ratio and AMAT.
A hazard is a dependency that stops the next instruction from entering its stage on time; structural, data, and control hazards are resolved by stalling, forwarding, branch prediction, or compiler reordering.