سوال ۸۱ کنکور ارشد مهندسی کامپیوتر ۱۴۰۱

The circuit is three $D$ flip-flops holding $A_2A_1A_0$, with a combinational next-state network feeding the $D$ inputs. Tracing the wires:

• The $A_0$ output runs up to the top rail, so the constant carry-in for bit 0 is effectively $1$. An inverter on the bit-0 line drives $D_0 = \overline{A_0} = A_0 \oplus 1.$
• The middle XOR takes $A_1$ and $A_0$ (the carry out of bit 0 is just $A_0$ when $c_{\text{in}}=1$): $D_1 = A_1 \oplus A_0.$
• The AND gate forms the carry into bit 2, $c_2 = A_1\cdot A_0$, and the left XOR gives $D_2 = A_2 \oplus (A_1\cdot A_0).$

These are exactly the equations of a ripple-carry increment-by-one network: each bit toggles iff all lower bits are $1$ (carry propagated). With carry chain $c_0=1,\; c_1=A_0,\; c_2=A_1A_0$ and $A_i' = A_i \oplus c_i$, the new state is $A' = A + 1 \pmod 8.$

Check $A = 011\;(=3)$: $D_0=\overline{1}=0,\quad D_1=1\oplus1=0,\quad D_2=0\oplus(1\cdot1)=1 \;\Rightarrow\; 100 = 4 = 3+1.\;\checkmark$ Check $A = 111\;(=7)$: $D_0=0,\;D_1=0,\;D_2=1\oplus1=0 \Rightarrow 000$, i.e. $7+1 \equiv 0 \pmod 8$. So the circuit is an up-counter that computes $A+1$.

Exam trick: Identify the carry pattern — bit $i$ flips when the AND of all lower bits is $1$ ($A_i\oplus(A_{i-1}\cdots A_0)$). Uncomplemented AND inputs mean increment ($+1$); complemented inputs (toggle on all-zeros below) would mean decrement ($-1$).